1. Field of the Invention
This invention relates to a data transmission apparatus which transmits and receives data between respective stations forming a communication system, and particularly to a data transmission apparatus which enables communications using different paths even if disconnection happens between a pair of stations.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional data transmission apparatus which is shown in Japanese Patent Laid-open No. 212047/1984. In FIG. 1, symbols a, e, and f denote a data transmission card as the data transmission apparatus, a system bus in a station, and a communication cable for connecting stations with one another, respectively. A numeral 1 is a microprocessor for transmission control of the data transmission card a, a numeral 2 is an internal bus of the microprocessor, a numeral 3 is a memory connected to the internal bus 2, a numeral 4 is an interface circuit (hereafter called I/F) which is connected to the internal bus and interfaces with the system bus e, a numeral 5 is an input/output circuit (hereafter called SIO) which is connected to the internal bus 2 and performs cross translation between a serial signal and a parallel signal, a numeral 6 is a direct memory access controller (hereafter called DMA) which is connected to the internal bus 2 and allows data to be directly exchanged between the microprocessor 1 and the SIO 5, a numeral 7 is a modulation circuit connected to the SIO 5, a numeral 8 is a demodulation circuit connected to the SIO 5, a numeral 9 is a solicit request signal sent to the modulation circuit 7 from the SIO 5, a numeral 10 is a transmitting clock sent to the modulation circuit 7 from the SIO 5 in the same way, a numeral 11 is serial transmitting data sent to the modulation circuit 7 from the SIO 5 in the same way, a numeral 12 is a receiving clock sent to the SIO 5 from the demodulation circuit 8, numeral 13 is a serial receiving data sent to the SIO 5 from the demodulation circuit 8, a numeral 14 is a driver for sending an output of the modulation circuit 7 to the communication cable f, and numeral 15 is a receiver for supplying an input from the communication cable f to the demodulation circuit 8.
FIG. 2 is a block diagram showing one example of stations constructed using such a data transmission card a. In FIG. 2, symbols b, c, and d are a CPU card, a memory card, and an IO card, respectively. These cards are connected to the system bus e together with the data transmission card a. Furthermore, FIG. 3 is a block diagram showing a communication system constructed by such a station. In FIG. 3, A, B, C, and D are stations described previously and are connected to each other by the communication cable f using a multi-drop system.
Next, the operation will be described. When data are transmitted from one station, for example, the station A, a solicit request for data transmission from the CPU card b is sent to the transmission card a by the system bus e, interfaced with the system bus e in the I/F, and transferred to the microprocessor 1 via the internal bus 2. The microprocessor 1 which has received this solicit request is set up for sending and sends a transmission starting signal to the SIO 5. The SIO 5 fetches transmitting data from the memory 3 using the DMA 6, converts them from parallel signals to serial signals, makes the solicit request signal 9 continuously active, and sends the transmitting clock 10 and the transmitting data 11 to the modulation circuit 7. In the modulation circuit 7, the received transmitting clock 10 and transmitting data 11 are modulated, converted into some modulated signals, and sent to the communication cable f via the driver 14.
The other stations B, C, and D receive the above-mentioned modulated signals from the communication cable f by the receiver 15 and send the received signals to the demodulation circuit 8. In the demodulation circuit 8, they are demodulated and separated into the receiving clock 12 and the receiving data 13, which are sent to the SIO 5. The SIO 5 converts them from serial signals to parallel signals. The received data are written in the memory 3 using the DMA 6 and, at the same time, this result is reported to the microprocessor 1 at the time point of termination of reception. The microprocessor 1 reports the result to the CPU card b from the I/F 4 via the system bus e.
In practical data transmission, these steps are executed through more complicated procedures including the use of addresses and the numbers of transmitting sources. But, since they are not directly related to this invention, they are omitted.
Since a conventional data transmission apparatus is constructed as described above, in the communication system adopting a multi-drop form, for example, when troubles in the communication cable f occur between the stations B ahd C, there is a problem that data transmission between the stations A and C, the stations A and D, the stations B and C, and the stations B and D are disabled. When the connection of a loop form is done by a communication cable shown by virtual line in FIG. 3, the influence due to reflections in the communication cable are increased at a transmission speed over 1 Mbps or so, thereby making it difficult to construct a practicable communication system.